Industry Experts Pessimistic on Success of Merced Chip

by Andy Santoni and Cara Cunningham, InfoWorld Electric

August 29, 1997
While Intel and its development partner Hewlett-Packard hinted about the details of the next-generation 64-bit "Merced" processor (speeds starting at 500 MHz with plans up to 4 GHz) to be available by the end of the decade, technologists met in Stanford, California this week to brainstorm how they hypothetically would design the chip. With all due seriousness, some concluded Intel should drop the whole thing.

Intel and Hewlett-Packard representatives didn't participate, but they were taking notes in the audience during a panel session at the HotChips IX conference.

The discussion elicited a range of bold comments. "I would cancel the whole Merced program," said Keith Diefendorff, a scientist at Apple Computer. Instead of developing the 64-bit Merced, Diefendorff would stick to the current 32-bit designs.

"I would milk that architecture for another 25 years," Diefendorff said.

Any advancements in design that Intel might implement in the Merced processor would add relatively little in performance, Diefendorff asserted. The performance to be gained by manufacturing technology changes such as moving to smaller feature sizes would eclipse the improvements gained by changes in architecture, according to Diefendorff.

Intel will unveil 0.25-micron technology on September 8 with the Tillamook Pentium processor and will use the same process in the Deschutes Pentium II processors the company will introduce early next year. Semiconductor equipment and device manufacturers are already working on 0.18-micron designs, and this technology should be available by the time Merced enters production in 1999.

The only reason for a new architecture is to follow a technology path, said Bruce Lightner, vice president of development at Metaflow Technologies. "It's time to move on to 64 bits," he said.

Users haven't even fully adopted 32-bit architectures, Lightner pointed out. "We're still running 16-bit code," he noted. Lightner would develop a new processor that uses a "virtual instruction set" to run existing software. By moving functions to software or firmware, the CPU would be able to run Intel x86 code, HP PA-RISC programs, or Java, for example.

Using software to emulate existing processors is a good idea, agreed Pete Wilson, an architecture specialist at Motorola Semiconductor. A pressing problem, Wilson said, is the increasing complexity of CPUs. This makes design time too long and leads to mistakes, he said.

"And things are going to get worse," Wilson said.

Another problem is that CPU speeds are increasing faster than memory speeds, Wilson said.

DRAM performance is falling behind, agreed Martin Reynolds, vice president of technology assessment at Dataquest, in San Jose, California. With memory-intensive applications such as 3D graphics becoming more common, faster access to memory is becoming more important.

Reynolds also agreed that the transition to Merced would not be quick. Merced CPUs will not replace the current generation of 32-bit processors until 2002 or later, he projected.

By then, users will be running 64-bit Windows NT on Merced, suggested John Novitsky, vice president of marketing at MicroModule Systems. Large database applications and large engineering design programs will move to the platform first, and it will take a long time for mainstream apps to go 64-bit, he agreed.

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